This disclosure relates in general to data processing and storage, and more specifically, to management of a data storage system, such as a flash memory system. Still more particularly, the present disclosure relates to management of a non-volatile memory system to reduce the read disturb effect on partially programmed blocks of non-volatile memory.
NAND flash memory is an electrically programmable and erasable non-volatile memory technology that stores one or more bits of data per memory cell as a charge on the floating gate of a transistor or a similar charge trap structure. In a typical implementation, a NAND flash memory array is organized in blocks (also referred to as “erase blocks”) of physical memory, each of which includes multiple physical pages each in turn containing a multiplicity of memory cells. By virtue of the arrangement of the word and bit lines utilized to access memory cells, flash memory arrays are generally programmed on a page basis, but are erased on a block basis.
As is known in the art, blocks of NAND flash memory must be erased prior to being programmed with new data. A block of NAND flash memory cells is erased by applying a high positive erase voltage pulse to the p-well bulk area of the selected block and by biasing to ground all of the word lines of the memory cells to be erased. Application of the erase pulse promotes tunneling of electrons off of the floating gates of the memory cells biased to ground to give them a net positive charge and thus transition the voltage thresholds of the memory cells toward the erased state. Each erase pulse is generally followed by an erase verify operation that reads the erase block to determine whether the erase operation was successful, for example, by verifying that less than a threshold number of memory cells in the erase block have been unsuccessfully erased. In general, erase pulses, of probably increasing amplitude or increasing duration or both, continue to be applied to the erase block until the erase verify operation succeeds or until a predetermined number of erase pulses have been used (i.e., the erase pulse budget is exhausted).
A NAND flash memory cell can be programmed (written) by applying a positive high program voltage to the word line of the memory cell to be programmed and by applying an intermediate pass voltage to the memory cells in the same string in which programming is to be inhibited. Application of the program voltage causes tunneling of electrons onto the floating gate to change its state from an initial erased state to a programmed state having a net negative charge. Each program pulse is generally followed by a program verify operation that reads the programmed cells to determine whether the program operation was successful, for example, by verifying that the memory cells under program have reached a specified program threshold voltage. In general, program pulses, of probably increasing amplitude or increasing duration or both, continue to be applied to the cells until the program verify operation succeeds or until a predetermined number of program pulses have been used.
A known source of reliability issues with NAND flash memory is a phenomenon known as a “read disturb” in which reading one set of cells (e.g., a row forming a physical page) impacts the threshold voltages of both read and unread cells in various rows of the same physical block of memory. This phenomenon is particularly pronounced for unread cells in the erased state. As a result of the shifts in the threshold voltage distributions of the unread cells, the bit error (BER) of the block may increase if a large number of reads are made to the block.
Typically, pages in the block are written sequentially based on the device-specific programming order, and vendors recommend that the programming of a block be finalized before any page is read from the block. However, this recommendation is not always observed, for example, because a NAND flash memory system that writes too many blocks in parallel to achieve high bandwidth may fill open blocks relatively slowly and therefore may not finalize all open blocks prior to allowing reads to the open blocks. If a large number of reads to an incomplete block are made, then the reliability of the data in the block can deteriorate due to the read disturb effect, particularly on those pages of the incomplete block that are not yet programmed, i.e., the pages of the incomplete block that are still in the erased state and will be programmed at a later point following any read accesses.